1. Field of the Invention
The present invention relates to a method of erasing data in a flash memory, and more particularly, to a method of respectively using a different erasing route to increase lifetime of the flash memory when erasing data.
2. Description of the Prior Art
In the modern information society, communicating mass information has become a regular part of life. To manage information efficiently, memory devices to access information have also become an area of development. Especially, flash memory with its advantages of low power consumption, high-speed operation, being readable/writable, non-volatile, and having no mechanical operations.
Flash memory comprises a plurality of memory units with each memory unit comprising a specially made MOS (Metal-Oxide-Semiconductor) transistor for storing bit digital data. Please refer to FIG. 1 of a diagram of a transistor 10 in a typical flash memory unit. In the transistor 10, an oxidative layer 16 of the transistor 10 further comprises a floating gate 14 barring a normal gate 12, a drain 18, a source 20, an oxidative layer 16, and a substrate 22. Although the detailed structure and physical mechanism differ with each kind of flash memory units, generally, when the flash memory operates(i.e. stores data), it injects an electric charge(usually, electrons) into the floating gate to change the threshold voltage of the transistor 10. The value of the threshold voltage represents the stored data in the memory unit corresponding to the transistor 10 is either 1 or 0.
To program new data into the flash memory, the original stored data in the flash memory has to be erased(i.e. the electric charges of the floating gate in each memory unit transistor are erased). If old data in the flash memory is not erased completely, remaining electric charges affect the threshold voltage, so programming new data correctly is unreliable. To ensure that old data is completely erased, a standard method is used. Please refer to FIG. 2 of a flow chart of an entire erasing process 30 in a prior art erasing method. The prior art erasing process 30 comprises:
Step 32: Start the entire erasing process. Set a value of a counter N to 0. Inject electric charges into the floating gates of all memory units to perform follow-up erasing steps.
Step 36: Perform the erasing process. The erasing process further comprises:
Step 38: Remove electric charges from the floating gate 12 along a fixed route.
Step 40: Verify whether the electric charges are completely removed from the floating gate of each transistor 10. Usually this step is performed by measuring the threshold voltage of the transistor 10. If the electric charges has been completely removed (or the remaining electric charges are lower than a tolerance), then the verification passes, and move on to step 42. If the verification is not successful, go to step 44.
Step 42: End of the erasing process 30.
Step 44: If erasing incomplete increase the counter N by 1 (N is the number of verification failures).
Step 46: Verify whether the value of the counter N is bigger than a default value Nf. If yes, the number of verification failures is too many, and the old data in the flash memory is incapable of being erased completely. If the value of the counter N is less than a default value Nf, another erasing process needs to be performed.
Step 48: A warning signal displays that the old data in the flash memory is not capable of being erased completely.
When performing the prior art erasing process, the electric charges in the floating gate 14 are removed along a fixed route in the transistor 10. Three routes are marked in FIG. 1, the three possible routes respectively are: Route 24 which is from the floating gate 14 to the channel, Route 26 which is from the floating gate 26 to the source 20, and Route 28 which is from the floating gate 14 to the drain 18. In the prior art erasing process, the electric charges in the floating gate 14 are moved out from the floating gate 14 along a fixed default route (using one of the above three possible routes). Since the floating gate is located at the oxidative layer 16, when the electric charges are moved out from the floating gate, the electric charges pass through the oxidative layer 16. After the flash memory erases data along a same route several times (when programming new data), the oxidative layer 16 on the route suffers damage and traps are produced, so that the electric charges sink into them and become trapped. By increasing the number of electric charges sinking into the oxidative layer 16 of the erasing route, the electric charges in the floating gate are more difficult to remove through this route. A saturation point occurs when the electric charges cannot be moved out via the route, and the prior art erasing method becomes inefficient and inadequate.
It is therefore a primary objective of the present invention to provide an erasing method of removing electric charges along different routes to erase old data to solve the above mentioned problems.
In a preferred embodiment, the present invention provides a method of erasing data in a flash memory. The flash memory comprises a plurality of memory units for storing data. The method comprises
repeatedly performing an erasing process along a erasing route to erase data stored in each memory unit; and
if after a predetermined number of erasing times, data in each memory unit is not completely erased, a second erasing route is utilized to perform the erasing process.
It is an advantage of the present invention that the erasing method can increase the endurance of the flash memory.
These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.